Digital data communication systems, subsystems, and devices transfer serial and/or parallel streams of data from one location to another. In typical applications, each digital data stream is associated with a companion clock signal to which the stream is referenced. The clock signal controls read/write timing for the given data stream. The characteristics of the clock or timing signals can vary to suit the particular application and the specific devices utilized by the system.
For certain applications, a clock signal is dedicated to the particular data set and the clock signal is only active during periods of data transference. Although the timing of the clock signal is related to the timing of the data, the timing of the clock signal need not be related to the timing of any other clock utilized by the system. For example, the clock signal may be asynchronous with reference clocks used by other devices in the system. This type of clock characteristic is commonly referred to as a gapped-clock; the following description refers to this clock characteristic as an asynchronous gated-clock.
An alternative data clocking technique employs an enabling signal that facilitates data transfer relative to and synchronously with a continuously active reference clock signal. The system devices monitor this enabling signal relative to the reference clock signal and, when the enabling signal represents an active state, read or write the accompanying data (at times dictated by the reference clock signal). This enabling signal is commonly referred to as a clock enable (or data enable); the following description refers to this signal characteristic as a synchronous clock-gate.
Conventional applications, e.g., a configuration having a host device that exchanges data with a plurality of target devices, may include a mix of synchronous and asynchronous target devices. In such an application, the host device provides a separate asynchronous gated-clock signal at one output port and a separate synchronous clock-gate signal at another output port. Additional clock signals generated at additional output ports may also be required to support devices that operate at different frequencies or utilize a variety of data bus types, e.g., bit-serial or a plurality of n-bit parallel data buses. Consequently, the number of clock signal ports on the host device increases and the manner in which the various clock signals are routed to the target devices can become complicated as more distinct clock signals are added.